CPU architecture overview

The Arm CPU architecture is implemented by a wide range of microarchitectures to deliver software compatibility across a broad range of power, performance, and area points. The architecture includes small implementations of Arm processors and efficient implementations of advanced designs.

  • The CPU architecture defines the basic instruction set, and the exception and memory models that are relied on by the operating system and hypervisor.
  • The CPU microarchitecture determines how an implementation meets the architectural contract. The microarchitecture defines the design of the processor, covering such things as: power, performance, area, pipeline length, and levels of cache.

Profiles, features, and related Arm IP

CPU architecture profiles A-profile R-profile M-profile
Use cases Used in complex compute application areas, such as servers, networking equipment, mobile phones, DTV, PCs, laptops, and automotive head units. Used where real-time response is required. For example, safety critical applications or applications needing a deterministic response, such as medical equipment or vehicle steering, braking and signaling. Used where energy efficiency, power consumption, and size are important. Deeply embedded chips and simple IoT devices are a key application of M-profile CPUs, for example, in small sensors, communication modules, and smart home products.
Arm implementation of the architecture profiles (Arm processor IP) Cortex-R Cortex-M

The Arm CPU architecture is based on Reduced Instruction Set Computer (RISC) principles and incorporates:

  • A uniform register file, where instructions were not restricted to acting on specific registers.
  • A load or store architecture, where data processing operated only on register contents, and not directly on memory contents.
  • Simple addressing modes, where all load or store addresses were only determined from register contents and instruction fields.


Optimized for high-level operating systems.

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Optimized for real-time high-performance applications.

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Optimized for discrete processing and microcontrollers.

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Debug Visibility and Trace

Debug visibility and trace for A-, R- and M-profiles.

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